1. Field of the Invention
The present invention relates to a display apparatus and, more specifically, to a technique for time-divisionally driving a plurality of data lines by a single amplifier.
2. Description of the Related Art
Due to the recent requirement of improved resolution, display panels are required to have an increased number of data lines (or signal lines), with reduced spacing between adjacent data lines. One problem caused by the increase in the number of signal lines and the decrease in the spacing therebetween is the difficulty in providing sufficient pitches for external wirings that provides electrical connections between data lines to a display panel driver. The decrease in the spacing between the data lines decreases the pitch allowed to the external wirings, which makes it difficult to connect the display panel with the display panel driver for driving the display panel. Another problem is the increase in the number of amplifiers used to drive the data lines within the display driver. The increase in the number of amplifiers undesirably makes the driver large-scaled and increases the cost of the display driver.
One approach for overcoming such problems it to time-divisionally drives a plurality of data lines by a single amplifier. For example, Japanese Laid-Open Patent Application No. Jp-A Heisei 11-327518 discloses a liquid crystal display apparatus that is designed to drive three data lines by a single amplifier.
FIG. 1 illustrates the structure of the liquid crystal display apparatus disclosed in this Japanese Laid-Open Patent Application. The liquid crystal display apparatus of FIG. 1 includes; a liquid crystal display panel 100; a common voltage generator circuit 104; a driver IC 107; and a switch control circuit 108. The liquid crystal display panel 100 includes: gate lines (scanning lines) 101: data lines 102R, 102G, and 102B; and a common electrode 103. Pixels are provided at respective intersections of the gate lines 101 and the data lines 102R, 102G, 102B. The gate lines 101 are driven by a vertical drive circuit 105. Switches 106R, 106G, and 106B are provided for the data lines 102R, 102G, and 102B, respectively, and each set of the switches 106R, 106G, and 106B are commonly connected to the same output of the driver IC. The switches 106R, 106G, and 106B are turned on and off by switch control pulses SL1, SL2, and SL3 received from a switch control circuit 108, respectively. The data lines to be driven are selected by the switches 106R, 106G, and 106B.
The driver IC 107 includes sampling circuits 111, memories 112, D/A converters 113, and output amplifiers 114. Pixel data of respective pixels (that is, data indicative of the grayscale levels of respective pixels) are sampled by the associated sampling circuits 111 and stored in the associated memories 112. The D/A converters 113 each generate an analog grayscale voltage corresponding to the image data stored in the associated memories 112. The output amplifiers 114 each drive the data line selected by the switches 106R, 106G, and 106B to the same drive voltages as the analog grayscale voltages received from the D/A converters 113.
FIG. 2 is a timing chart illustrating the operation of the liquid crystal display apparatus of FIG. 1, particularly the procedure of driving three target pixels positioned at the intersections of the data lines 102Rn, 102Gn, and 102Bn and the gate line 101m. The three target pixels are driven through the following procedure. After the voltage Vg of the gate line 101m is pulled up to “High” level, the switch control pulses SL1, SL2, and SL3 are successively supplied to successively turn on the switches 106Rn, 106Gn, and 106Bn. Simultaneously with the turn-on of the switches 106Rn, 106Gn, and 106Bn, drive voltages are successively supplied from the driver IC 107 to the data lines 102Rn, 102Gn, and 102Bn. After the data lines 102Rn, 102Gn, and 102Bn are driven, the switches 106Rn, 106Gn, and 106Bn are turned off. Through this procedure, the drive voltages are successively written into the three pixels at the intersections of the data lines 102Rn, 102Gn, and 102Bn and the gate line 101m. 
Japanese Laid-Open Patent Application No. Jp-A 2005-43418 discloses another liquid crystal display apparatus designed to drive three data lines by a single amplifier. FIG. 3 is a block diagram illustrating the structure of the liquid crystal display apparatus disclosed in this Japanese Laid-Open Patent Application. This liquid crystal display apparatus is configured to precharge all of the data lines to a predetermined amendment voltage Vamd before actually driving the data lines so as to suppress vertical crosstalk (display unevenness in the direction along the data lines). The data line precharge is also effective to reduce the power consumption of the liquid crystal display apparatus.
More specifically, the liquid crystal display apparatus of FIG. 3 includes: a display panel 201; a gate line drive circuit 203; a data line drive circuit 204; a control circuit 205; and a frame memory 206. The display panel 201 includes data lines X1 to Xm and gate lines Y1 to Yn, and pixels 202 are provided at respective intersections of the data lines X1 to Xm and the gate lines Y1 to Yn. The gate line drive circuit 203 drives the gate lines Y1 to Yn, while the data line drive circuit 204 drives the data lines X1 to Xm. The data line drive circuit 204 includes a driver IC 241 and a time-division circuit 242. The driver IC 241 includes output lines DO1 to DOi, and every three data lines are connected to the same output line through the time-division circuit 242. The time-division circuit 242 includes three switches 243, 244, and 245 for each of the every three data lines. The switches 243, 244, and 245 connect or disconnect the three data lines to/from the associated output pins in response to selection signals SS1, SS2, and SS3 received from the control circuit 205, respectively.
FIG. 4 is a timing chart illustrating the operation of the liquid crystal display apparatus of FIG. 3, particularly, the procedure for driving three pixels positioned at the intersections of the data lines X1 to X3 and the gate line Y1. The three pixels are driven through the following procedure. After activation of the gate line Y1, all the control signals SS1 to SS3 are pulled up to the “High” level to turn on the switches 243, 244, and 245. The turn-on of the switches 243, 244, and 245 allows the data lines X1 to X3 to be electrically connected with the output pin PIN1 of the driver IC 241. The amendment voltage Vamd is then outputted from the output line DO1 with the switches 243, 244, and 244 turned on, so that the data lines X1 to X3 are precharged to the amendment voltage Vamd. Thereafter, the control signals SS1 to SS3 are all pulled down to the “Low” level. This is followed by successively pull up the control signals SS1 to SS3 to the “High” level to successively turn on the switches 243, 244, and 245. Simultaneously with the turn-on of the switches 243, 244, and 245, drive voltages are then successively supplied from the driver IC 241 to the data lines X1 to X3. After the data lines X1 to X3 are driven, the switches 243, 244, and 245 are turned off. Through this procedure, the drive voltages are written to the three pixels positioned at the intersections of the data lines X1 to X3 and the gate line Y1.
However, the liquid crystal display apparatuses shown in FIGS. 1 and 3 suffer from such a problem that increased electric power is consumed in the switches used for selecting the data lines (that is, the switches 106R, 106G, 106B in FIG. 1, and the switches 243, 244, 245 in FIG. 3). The electric power Q consumed in a single switch is expressed with a following formula:Q=CG×VG×(f×r)×VG,  (1)where CG (pF) is the sum of the gate capacitance and the capacitance of the interconnections connected to the gates of the switches, VG is the voltage applied to the gates, f (Hz) is the frame frequency (frame rate), and m is the number of lines (number of gate lines). As understood from the formula (1), the electric power consumed in the switch is proportional to the sum of the gate capacitance and the interconnection capacitance, and is also proportional to the square of the voltage applied to the gate of the switches.
Unpreferably, TFTs (thin film transistors), which have a large gate capacitance, are usually used as the switches for selecting the data lines, and the voltage applied to the gate is inevitably high. The TFTs are requested to have a high drive ability for driving the long data lines, and this requires the TFTs to have a large gate width. Thus, the gate capacitance thereof is inevitably large. In addition, the drive voltage of the pixels may reach as high as about 20V, and this requires applying high voltage of about 20V to the gates of the TFTs. Therefore, as understood from the formula (1), the power consumption of the switches used for selecting the data lines may be unacceptably increased. The increased power consumption is an issue particularly when the liquid crystal display apparatus is used within a portable electronic device.